Abstract:
An analog-to-digital converter (ADC), which can be either continuous or discrete
in nature, is a crucial component of a signal processing system. An oversampling ADC
is currently an effective option for data converters due to its compact silicon area, low
power requirement, and greater resolution as opposed to standard ones with Nyquist
frequency limit. The oversampling ADCs sample analog signals at a rate that is higher
than the Nyquist rate and is typically expressed as OSR. Also, they are particularly
preferred for high-speed applications due to their relative simplicity and resilience
to component mismatch and circuit faults. Using basic analog circuitry, the Delta Sigma ADC pushes noise to high frequency using oversampling and noise-shaping
technologies. Its SNR and precision are higher than those of other conventional ADCs.
To satisfy the objectives of an efficient design, the decimation filter, which is a
crucial component of ADCs, needs to be improved in various areas. The first and
second-order delta-sigma modulators are developed. It has been found that com pared to the 1st-order Delta-Sigma modulator, the 2nd-order Delta-Sigma modulator
offers greater stability and noise immunity. This work proposes a new method for
implementing a high-performing, low-power Second Order Delta-Sigma digital dec imation filter. A Cascaded Integrated Comp (CIC) filter and a Biquad filter make
up the Digital Decimation filter. The Second-order Delta-Sigma Decimation Filter is
designed and modeled using Simulink. The proposed ADC achieves an SNR of 73.46
dB and an ENOB of 11.91. The post-simulation demonstrates that the suggested
ADC provides a Spurious Free Dynamic Range of 95.38 dB.
